View ISL90726UIE627Z-TK_4871305.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL90726
Single Volatile 128-Tap XDCPTM
Data Sheet August 26, 2008 FN8244.4
Digitally Controlled Potentiometer (XDCP)
The Intersil ISL90726 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, and a control section. The wiper position is controlled by an I2C interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the SDA and SCL inputs.
Features
* Volatile Solid-State Potentiometer * I2C Serial Bus Interface * DCP Terminal Voltage, 2.7V to 5.5V * Low Tempco - Rheostat - 45 ppm/C typical - Divider - 15 ppm/C typical * 128 Wiper Tap Points - Wiper Resistance 70 typ at VCC = 3.3V * Low Power CMOS - Active Current, 200A Max - Standby Current, 500nA Max * Available RTOTAL Values = 50k, 10k
Pinout
ISL90726 (6 LD SC-70) TOP VIEW
VDD 1 GND 2 SCL 3 6 RL 5 RW 4 SDA
* Power on Preset to Midscale * Packaging - 6 Ld SC-70 * Pb-Free (RoHS compliant)
Applications
* Mechanical Potentiometer Replacement * Transducer Adjustment of Pressure, Temperature, Position, Chemical, and Optical Sensors * Laser Diode and LED Biasing * LCD Brightness and Contrast Adjustment * Gain Control and Offset Adjustment * DDR3 Margining
Ordering Information
PART NUMBER (Note) ISL90726WIE627Z-TK* ISL90726UIE627Z-TK* PART MARKING ANF ANG RTOTAL (k) 10 50 TEMP RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 6 Ld SC-70 6 Ld SC-70 PKG. DWG. # P6.049 P6.049
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL90726 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 SYMBOL VDD GND SCL SDA RW RL Supply Voltage Ground Open drain Serial Clock input Open drain Serial Data I/O Potentiometer Wiper Terminal Potentiometer End Terminal DESCRIPTION
Block Diagram
VDD RH SCL SDA I2C INTERFACE RW
WIPER REGISTER
RL
GND
2
FN8244.4 August 26, 2008
ISL90726
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Voltage at any DCP Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 6 Ld SC-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W, U versions respectively -20 VCC = 3.3V @ +25C 85 10/10/25 Voltage at pin from GND to VCC 0.1 1 MIN (Note 12) TYP (Note 2) 10, 50 +20 MAX (Note 12) UNIT k % pF A
PARAMETER RH to RL Resistance RH to RL Resistance Tolerance
RW CH/CL/CW ILkgDCP
Wiper Resistance Potentiometer Capacitance Leakage on DCP Pins
RESISTOR MODE RINL (Note 7) Integral Non-linearity DCP register set between 20 hex and 7F hex. Monotonic over all tap positions (Note 3) DCP register set between 20 hex and 7F hex. Monotonic over all tap positions (Note 3) W option U option -2 -1 -1 0 0 0.25 0.1 0.1 1 0.5 45 2 1 1 3 2 MI (Note 4) MI (Note 4) MI (Note 4) MI (Note 4) MI (Note 4) ppm/C
RDNL (Note 6) Differential Non-linearity
ROFFSET (Note 5)
Offset
W option U option
TCR (Notes 8, 9)
Resistance Temperature Coefficient
DCP register set between 20 hex and 7F hex (Note 3)
Operating Specifications
SYMBOL ICC1 ISB IComLkg tDCP (Note 9) VCCRamp PARAMETER VCC Supply Current (Volatile Write/Read) VCC Current (Standby) Common-Mode Leakage DCP Wiper Response Time TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Volatile Write States only) VCC = +5.5V, I2C Interface in Standby State Voltage at SDA pin at GND or VCC SCL falling edge of last bit of DCP Data Byte to wiper change 0.2 500 MIN (Note 12) TYP (Note 2) MAX (Note 12) UNIT 200 A
500 3
nA A ns
VCC Ramp Rate
V/ms
3
FN8244.4 August 26, 2008
ISL90726
Operating Specifications
SYMBOL tD (Continued) TEST CONDITIONS VCC above VPOR, to DCP Initial Value Register recall completed, and I2C Interface in standby state MIN (Note 12) TYP (Note 2) MAX (Note 12) UNIT 3 ms
PARAMETER Power-up Delay
SERIAL INTERFACE SPECIFICATIONS VIL (Note 10) VIH (Note 10) Hysteresis SDA, and SCL Input Buffer LOW Voltage SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. -0.3 0.3*VCC VCC + 0.3 V
0.7*VCC 0.05*VCC 0
V
V
VOL Cpin (Note 9) fSCL tIN tAA tBUF
0.4
V
10 400 50
pF kHz ns
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VCC, until Data Valid SDA exits the 30% to 70% of VCC window. Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC From 70% to 30% of VCC 1300
900
ns
ns
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600
ns ns ns
START Condition Hold Time
600
ns
Input Data Setup Time
100
ns
tHD:DAT tSU:STO tHD:STO tDH
Input Data Hold Time
0
ns
STOP Condition Setup Time
600
ns
STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600
ns
0
ns
tR (Note 11) tF (Note 11)
SDA and SCL Rise Time
20 + 0.1*Cb 20 + 0.1*Cb
250
ns
SDA and SCL Fall Time
250
ns
4
FN8244.4 August 26, 2008
ISL90726
Operating Specifications
SYMBOL Cb (Note 11) (Continued) TEST CONDITIONS Total on-chip and off-chip MIN (Note 12) 10 TYP (Note 2) MAX (Note 12) UNIT 400 pF
PARAMETER Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip
Rpu (Note 11)
Maximum is determined by tR and tF. For Cb = 400pF, max is about 2k ~ 2.5k. For Cb = 40pF, max is about 15k ~ 20k.
1
k
NOTES: 2. Typical values are for TA = +25C and 3.3V supply voltage. 3. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 4. MI = |R127 - R0|/127. R127 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. ROFFSET = R0/MI, when measuring between RW and RL. 5. ROFFSET = R127/MI, when measuring between RW and RH. 6. RDNL = (Ri - Ri-1)/MI, for i = 32 to 127. 7. RINL = [Ri - (MI * i) - R0]/MI, for i = 32 to 127. 6 [ Max ( Ri ) - Min ( Ri ) ] 10 8. TC = --------------------------------------------------------------- x -------------------- for i = 32 to 127, T = -40C to +85C. Max( ) is the maximum value of the resistance and Min ( ) is R [ Max ( Ri ) + Min ( Ri ) ] 2 +125C the minimum value of the resistance over the temperature range. 9. This parameter is not 100% tested. 10. VIL = 0V, VIH = VCC. 11. These are I2C-specific parameters and are not directly tested. However, they are used in the device testing to validate specifications. 12. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Principles of Operation
The ISL90726 is an integrated circuit incorporating one DCP with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 7-bit volatile Wiper Register (WR). The DCP has its own WR. When the WR of the DCP contains all zeroes (WR<6:0> = 00h), its wiper 5
terminal (RW) is closest to its "Low" terminal (RL). When the WR of the DCP contains all ones (WR<6:0> = 7Fh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. RH is not connected to a device pin. The net effect is the resistance between RW and RL increases monotonically. While the ISL90726 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections.
FN8244.4 August 26, 2008
ISL90726 I2C Serial Interface
The ISL90726 supports bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90726 operates as slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. A valid Identification Byte contains 0101110 as the seven MSBs. The LSB in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (see Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 1 1 0 R/W (LSB)
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90726 responds with an ACK. At this time, the device enters its standby state (see Figure 3).
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 1). On power-up of the ISL90726, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90726 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 1). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 1). An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 2). The ISL90726 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90726 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation.
Data Protection
A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and nonvolatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0h, the Data Byte is transferred to the Wiper Register (WR) at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If an address other than 00h, or an invalid slave address is sent, then the device will respond with no ACK.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 4). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL90726 responds with an ACK. Then the ISL90726 transmits the Data Byte as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (see Figure 4).
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
6
FN8244.4 August 26, 2008
ISL90726
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL23711
01 01 1 100 A C K
0000 0 000 A C K A C K
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W = 1
S T O P
SIGNAL AT SDA
01011100 A C K
00000000 A C K
01011101 A C K
SIGNALS FROM THE SLAVE
DATA BYTE
FIGURE 4. READ SEQUENCE
7
FN8244.4 August 26, 2008
ISL90726 Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M C L b e C VIEW C
P6.049
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053 MILLIMETERS MIN 0.80 0.00 0.00 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 NOTES -
6 C L 1
5
4 C L E E1
A A1 A2 b b1 c c1 D E E1 e e1 L L1 L2 N R
2
3
e1 D C L
C
A
A2
A1
SEATING PLANE -C-
0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 6 0.004 0.004 0o 0.010 8o
0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 6 0.10 0.15 0o 0.25 8o
0.10 (0.004) C
WITH PLATING c
b b1 c1
5
R1
BASE METAL
Rev. 2 9/03
NOTES:
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C L1
1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN8244.4 August 26, 2008

▲Up To Search▲

Price & Availability of ISL90726UIE627Z-TK

	To Download ISL90726UIE627Z-TK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .